Forum Discussion
Altera_Forum
Honored Contributor
15 years agoTo add more:
First you need to define your VHDL module Inputs/outputs. I suggest these as possible candidates, plus others as needed: inputs: reset (std_logic) clk (std_logic) car_in(std_logic) car_out(std_logic) midnight_sync(std_logic) outputs: error(std_logic) full(std_logic) empty(std_logic) number_of_cars_in(std_logic_vector(1023 downto 0) With regard to time of entry etc. You will need to have a separate module to generate time clock.