vhdl-car park monitoring system

i ve done this so far:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity counter is

generic (n:natural:=1024);

port ( c, clk:in std_logic;

reset;in std_logic;

cout: out std_logic_vector( 1023 downto 0);

end counter

architecture behv of counter is

begin

process (clk, reset, cout)

begin

if (reset='1') then

cout<=(others=>'0');

elsif ( rising_edge(clk)) then

if (up_down='1') then

count <=count+1

else

count<=count-1

end if;

end if;

end process;

cout<=count;

end architecture;

synchronous reset with clock enable;

process (clk)

begin

if rising_edge(clk) then

if enable='1' then

Q<=D;

end if;

end if;

if reset='1' then

Q<='0';

end if;

end process;