VHDL bug in Altera tools?

Hi,

according to the VHDL standard, functions and procedures are allowed to call other functions and procedures. Unfortunately, the following piece of code does not behave as expected when comiled with Quartus 11.1:

library ieee;

use ieee.std_logic_1164.all;

entity bug_or_feature is

port(

input : in std_logic;

output: out std_logic );

procedure nestedAssert( s: string ) is

begin

assert false report s severity warning;

end procedure nestedAssert;

procedure plainAssert( s : string ) is

begin

nestedAssert( "this does not work: " & s );

assert false report "this works: " & s severity warning;

end procedure plainAssert;

begin

plainAssert( "plainAssert" );

nestedAssert( "nestedAssert");

end entity bug_or_feature;

architecture arch of bug_or_feature is

begin

output <= not input;

end architecture arch;

During compilation, I expect three warnings. First, I call plainAssert, which throws one warning "this works: plainAssert" and should call nestedAssert to throw the second warning "this does not work: plain Assert". Second, a direct call to nestedAssert should throw the third warning "nested Assert". However, I just get the warnings "this works: plainAssert" and the warning "nestedAssert".

The question is, why does plainAssert not process the call to nesetedAssert during compilation?