VHDL array syntax

I'm just trying to test out writing out arrays in VHDL but I can't get it to work. The error I get is Error (10568): VHDL error at Testarray.vhd(16): can't write to interface object "a" of mode IN

Library ieee;

USE ieee.std_logic_1164.all;

ENTITY arraytest is

PORT (

a : IN STD_LOGIC_VECTOR (3 downto 0);

z : OUT STD_LOGIC

);

END;

ARCHITECTURE assignment OF arraytest is

BEGIN

a <= "1100";

z <= a(0) and a(1);

END;

Thanks.