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Honored Contributorvhdl 4 bit 7 segment display
hello,
How to display BCD in 7-segment. i'm trying to display clock value on 4 7segment displays via bcd to 7 segment decoder(4511n). any can someone tell whats going wrong. 7 segment do not display any values!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity DIGI_KLOK is
port (
Dselect : in std_logic;
D_Display : in std_logic_vector(3 downto 0);
D_Select : out std_logic_vector(3 downto 0)
);
end DIGI_KLOK;
component Tijd_Converter
port (
Con_In_m : integer range 0 to 59;
Con_In_h : integer range 0 to 23;
Con_out_1, Con_out_2, Con_out_3, Con_out_4 : out std_logic_vector(0 to 3)
);
end component;
architecture Behavioral of DIGI_KLOK is
signal Clock : std_logic := '0';
signal teller : integer := 1;
signal second : integer range 0 to 59;
signal minute : integer range 0 to 59;
signal hour : integer range 0 to 23;
signal Output_1, Output_2, Output_3, Output_4 : std_logic_vector(3 downto 0);
component Updade_Display
port (
D_Display : in std_logic_vector(3 downto 0);
D_Select : out std_logic_vector(3 downto 0)
);
end component;
begin
process(Dselect)
begin
if rising_edge(Dselect) then
teller <= teller + 1;
if(teller = 5000000) then
Clock <= not Clock;
teller <=1;
end if;
end if;
end process;
process(Clock)
begin
if(Clock'event and Clock='1') then
second <= second + 1;
if(second = 59) then
minute <= minute + 1;
if(minute = 59) then
hour <= hour + 1;
minute <= 0;
if(hour = 23) then
hour <= 0;
end if;
end if;
end if;
end if;
end process;
Block_Converter: Tijd_Converter port map (Input_1, Input_2, Output_1, Output_2, Output_3, Output_4);
Block_PinOuts0: Updade_Display port map (Output_1, D_Select);
Block_PinOuts1: Updade_Display port map (Output_2, D_Select);
Block_PinOuts2: Updade_Display port map (Output_3, D_Select);
Block_PinOuts3: Updade_Display port map (Output_4, D_Select);
end Behavioral;
library ieee;
use ieee.std_logic_1164.all;
-- --------------------------------------------------------------------------
entity Updade_Display is
port (
D_Display : in std_logic_vector(3 downto 0);
D_Select : out std_logic_vector(3 downto 0)
);
end Updade_Display;
-- --------------------------------------------------------------------------
architecture Behavior of Updade_Display is
begin
D_Select <= "0000" when (D_Display = "0000") else -- 0
"0001" when (D_Display = "0001") else -- 1
"0010" when (D_Display = "0010") else -- 2
"0011" when (D_Display = "0011") else -- 3
"0100" when (D_Display = "0100") else -- 4
"0101" when (D_Display = "0101") else -- 5
"0110" when (D_Display = "0110") else -- 6
"0111" when (D_Display = "0111") else -- 7
"1000" when (D_Display = "1000") else -- 8
"1001" when (D_Display = "1001") else -- 9
null;
end Behavior;
library ieee;
use ieee.std_logic_1164.all;
-- --------------------------------------------------------------------------
entity Tijd_Converter is
port (
Con_In_m : integer range 0 to 59;
Con_In_h : integer range 0 to 23;
Con_out_1, Con_out_2, Con_out_3, Con_out_4 : out std_logic_vector(0 to 3)
);
end Tijd_Converter;
-- --------------------------------------------------------------------------
architecture Behavior of Tijd_Converter is
begin
process(Con_In_m, Con_In_h)
begin
if Con_In_m = 0 then
Con_out_3 <= "0000";
Con_out_4 <= "0000";
Con_out_1 <= "0000";
Con_out_2 <= "0000";
elsif Con_In_m = 1 then
Con_out_1 <= "0001";
Con_out_2 <= "0000";
elsif Con_In_m = 2 then
Con_out_1 <= "0010";
Con_out_2 <= "0000";
elsif Con_In_m = 3 then
Con_out_1 <= "0011";
Con_out_2 <= "0000";
elsif Con_In_m = 4 then
Con_out_1 <= "0100";
Con_out_2 <= "0000";
elsif Con_In_m = 5 then
Con_out_1 <= "0101";
Con_out_2 <= "0000";
elsif Con_In_m = 6 then
Con_out_1 <= "0110";
Con_out_2 <= "0000";
elsif Con_In_m = 7 then
Con_out_1 <= "0111";
Con_out_2 <= "0000";
elsif Con_In_m = 8 then
Con_out_1 <= "1000";
Con_out_2 <= "0000";
elsif Con_In_m = 9 then
Con_out_1 <= "1001";
Con_out_2 <= "0000";
elsif Con_In_m = 10 then
Con_out_1 <= "0000";
Con_out_2 <= "0001";
elsif Con_In_m = 11 then
Con_out_1 <= "0001";
Con_out_2 <= "0001";
elsif Con_In_m = 12 then
Con_out_1 <= "0010";
Con_out_2 <= "0001";
elsif Con_In_m = 13 then
Con_out_1 <= "0011";
Con_out_2 <= "0001";
elsif Con_In_m = 14 then
Con_out_1 <= "0100";
Con_out_2 <= "0001";
elsif Con_In_m = 15 then
Con_out_1 <= "0101";
Con_out_2 <= "0001";
elsif Con_In_m = 16 then
Con_out_1 <= "0110";
Con_out_2 <= "0001";
elsif Con_In_m = 17 then
Con_out_1 <= "0111";
Con_out_2 <= "0001";
elsif Con_In_m = 18 then
Con_out_1 <= "1000";
Con_out_2 <= "0001";
elsif Con_In_m = 19 then
Con_out_1 <= "1001";
Con_out_2 <= "0001";
elsif Con_In_m = 20 then
Con_out_1 <= "0000";
Con_out_2 <= "0010";
elsif Con_In_m = 21 then
Con_out_1 <= "0001";
Con_out_2 <= "0010";
elsif Con_In_m = 22 then
Con_out_1 <= "0010";
Con_out_2 <= "0010";
elsif Con_In_m = 23 then
Con_out_1 <= "0011";
Con_out_2 <= "0010";
elsif Con_In_m = 24 then
Con_out_1 <= "0100";
Con_out_2 <= "0010";
end if;
end process;
end Behavior;
