vhdl -division program

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In the meantime I checked this point, and I found, that the integrity of the divider IP isn't touched by the compiler/fitter. No available register is moved into the divider logic. I think it can be understood from the fact, that the divider inference doesn't provide the option to connect a clock, so it can't use the pipeline option.

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i do see registers get moved into internal divider logic.

i am using Altera's signed I/O registered multiplier VHDL template as a reference (multiply changed to divide). i was using 40 bit input and outputs for this test. first run achieves 4.83 MHz (CIII -8). adding an extra input stage of input registers gets the design to 6.41 MHz. that's a 33% improvement! adding another stage of input registers does not improve performance, which is the part i found interesting. maybe worth an enhancement request.

either way the lpm_divide still wins with 2 pipeline stages somewhere in the 10 MHz range. :eek: