vhdl -division program

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it would be nice if register retiming could meet the fmax of an lpm function.

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In the meantime I checked this point, and I found, that the integrity of the divider IP isn't touched by the compiler/fitter. No available register is moved into the divider logic. I think it can be understood from the fact, that the divider inference doesn't provide the option to connect a clock, so it can't use the pipeline option.

Regarding the suggestion to replace a division by a multiply. I'm using this in two situations:

- when the divisor is a constant, as discussed above

- when the divisor is a signal, but can tolerate a larger latency time than the dividend. Then 1/b can be calculated by a slow serial divider and multiplied with a in a single clock cycle.

If both a and b must be processed with low latency time, it doesn't work.