VGA controller in Verilog

I've been trying to code a simple VGA controller to run on my

Altera DE1 board. Here is my code:

`define rgb {vga_r, vga_g, vga_b}
`define rgb_gnd {12{gnd}}
`define red {4'd15, 4'd0, 4'd0}
`define white {4'd15, 4'd15, 4'd15}
`define other {4'd3, 4'd7, 4'd8}
`define reset ~key
/* states: */
`define vertical_sync 4'd0
`define vertical_front_porch 4'd1
`define vertical_back_porch 4'd2
`define horizontal_sync 4'd3
`define horizontal_front_porch 4'd4
`define pixels_driving 4'd5
`define horizontal_back_porch 4'd6
/*~~~~~~~~~~*/
/* all following counts have 1
* subtracted from them to compensate
* for starting to count from 0 */
`define max_pulse_count 10'd798
`define max_line_count 10'd524
`define max_vertical_sync_count 10'd1
`define max_vertical_front_porch_count 10'd34
`define max_vertical_c_count 10'd514
`define max_vertical_back_porch_count 10'd524
`define max_horizontal_sync_count 10'd95
`define max_horizontal_front_porch_count 10'd143
`define max_pixels_driving_count 10'd783
`define max_horizontal_back_porch_count 10'd798
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
module vga(
        vga_r, vga_g, vga_b,
        vga_hs, vga_vs,
        clock_50,
        key
    );
    output reg  vga_r, vga_g, vga_b;
    output reg vga_hs, vga_vs;
    input clock_50;
    input  key;
    reg clock_25;
    /* pulse_count counts for each clock pulse
    while line_count counts for each line of the display */
    reg  pulse_count, line_count;
    reg  next_state;
    reg  vga_counter;
    supply0 gnd;
    
    always @(posedge clock_50) begin
        clock_25 <= ~clock_25;
    end
    always @(posedge clock_25) begin
        if (`reset) begin
            next_state <= `vertical_sync;
            pulse_count <= 10'd0;
            line_count <= 10'd0;
        end
        else begin
            vga_counter <= vga_counter + 4'd1;
            vga_vs <= 1'b1;
            vga_hs <= 1'b1;
            `rgb <= `rgb_gnd;
            if (pulse_count == `max_pulse_count) begin
                pulse_count <= 10'd0;
                if (line_count == `max_line_count) 
                    line_count <= 10'd0;
                else
                    line_count <= line_count + 10'd1;
            end
            else
                pulse_count <= pulse_count + 10'd1;
            // state machine
            case (next_state)
                `vertical_sync: begin
                    vga_vs <= 1'b0;
                    if (line_count == `max_vertical_sync_count && pulse_count == `max_pulse_count)
                        next_state <= `vertical_front_porch;
                end
                `vertical_front_porch: begin
                    if (line_count == `max_vertical_front_porch_count && pulse_count == `max_pulse_count)
                        next_state <= `horizontal_sync;
                end
                `horizontal_sync: begin
                    vga_hs <= 1'b0;
                    if (pulse_count == `max_horizontal_sync_count)
                        next_state <= `horizontal_front_porch;
                end
                `horizontal_front_porch: begin
                    if (pulse_count == `max_horizontal_front_porch_count)
                        next_state <= `pixels_driving;
                end
                `pixels_driving: begin
                    `rgb <= `white;
                    if (pulse_count == `max_pixels_driving_count)
                        next_state <= `horizontal_back_porch;
                end
                `horizontal_back_porch: begin
                    if (pulse_count == `max_horizontal_back_porch_count)
                        if (line_count == `max_vertical_c_count)
                            next_state <= `vertical_back_porch;
                        else
                            next_state <= `horizontal_sync;
                end
                `vertical_back_porch: begin
                    if (line_count == `max_vertical_back_porch_count && pulse_count == `max_pulse_count)
                        next_state <= `vertical_sync;
                end
            endcase
        end
    end
endmodule

Note that my board has a DAC which converts the 4-bit digital

signal for each of the RGB colors to the analog signal required

by VGA.

When I run this code the monitor leaves the "No Signal Found"

indication but it stays black no matter which color I choose.

I know that the board works because the VGA output works fine

with the demonstration provided by Altera.

Any help greatly appreciated.