Honored Contributor
Honored ContributorNow that you mention fifo's.. I would like to expand my current design.
In the 100MHz clock domain, I need to generate pixel data based on video ram (also clocked at 100MHz). However, I need a pixel (x, y) coordinate to calculate what color the pixel should be. Currently, the (x, y) pixel coordinate is coming from the VGA controller, which is clocked at 25.175 MHz, so I can't let it cross the 100MHz clock domain without some delay. My idea right now is to use a asynchronous FIFO (dcfifo), and simulate the (x, y) coordinate in the 100MHz clock domain. The 100MHz clock will check the "wrfull" signal of the fifo, and only write a pixel to the fifo when the fifo is not full, and in that case, it will also advance the (x,y) coordinate. The VGA clock will check the "rdempty" signal of the fifo, and feed the color from the fifo to the VGA output (the fifo should always be non-empty, since the 100MHz clock will make sure of that). However, the problem I can foresee is, how do I synchronize the simulated (x, y) coordinate, with the real vga_x and vga_y? Maybe I can somehow reset it during vsync in one way or another? And, will things be still sychronized in case of a system reset? What if the FIFO was not empty, and adds some extra delay?
