VGA 25MHz, Clock 100MHz, Help!

clk is not vga_clk

clk is ~100MHz

vga_clk ~25MHz

in your design the two clocks are different ! so you must obey them and perform clock domain crossing

first some verilog hints from my side

within always construct use <= (non-blocking assignment)

instead of = (blocking assignment)

second, the compare "vga_y == 0" is correct s long as vga_y is 1 bit wide. if it is an array better use === you will waste lot of time hunting such a bug when using == with arrrays

so your code a bit shorted

always @ ( posedge clk )

counter <= counter + 1;

and

always @ ( posedge clk )

vga_color <= counter

shows one problem.

counter is based on a different clock that vga_color, so you could get some glitches and oll other problems.

the synchronisation is exactly described by the quartus online help, but it says something like taht for your problem

reg [31:0] counter_piped1;

reg [31:0] counter_piped2;

always @ ( posedge vga_clk)

begin

counter_piped1 <= counter;

counter_piped2 <= counter_piped1;

end

(you recognized the 2 DFF here both 32bit wide ?)

now counter_piped2 is syncron with vga_clk

always @ ( posedge vga_clk)

vga_color <= counter_piped2;