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Honored Contributor
Honored ContributorVery simple question, first time using Verilog here...
Hello all... My name is Craig and this is my first post. I just started taking a course in HDL using Verilog. I've been beating my head against the wall for days over a very simple proble...
Altera_ForumHonored Contributor
Honored ContributorI hope you don't expect this code to be systhesizable into an FPGA or whatever. It is not. Concerning the logical function please note that the relevant code lines are inside an initial statement and, thus, will only be executed once. Use a statement that triggers these lines every time an input signal changes.
