Very low speed of HPS after Preloader

In cv_5v4.pdf ("Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference") is subsection cv_54002: "Clock Manager", and writed:

--- Quote Start ---

The Clock Manager offers the following features:

• Generates and manages clocks in the HPS

• Contains the following PLL clock groups:

- Main—contains clocks for the Cortex-A9 microprocessor unit (MPU) subsystem, level 3 (L3)

interconnect, level 4 (L4) peripheral bus, and debug

- Peripheral—contains clocks for PLL-driven peripherals

- SDRAM—contains clocks for the SDRAM subsystem

...

--- Quote End ---

In example Altera-SoCFPGA-HardwareLib-ClockManager-CV-GNU to console is outed 25 MHz for HPS and other, I try use the code:

    my_chk(); {
      uint32_t mu, di;
      status = alt_clk_pll_vco_cfg_get(ALT_CLK_MAIN_PLL, &mu, &di);
      if (status == ALT_E_SUCCESS) {
    	status = alt_clk_pll_vco_cfg_set(ALT_CLK_MAIN_PLL, mu*2, di);
        if (status == ALT_E_SUCCESS) {
          my_chk();
        }
      }
    }

to increase speed of HPS, however call of alt_clk_pll_vco_cfg_set() return error !

And what is more -- call of "alt_clk_pll_vco_cfg_set(ALT_CLK_MAIN_PLL,mu,di);" (without "*2") also return error ! Mistake is in alt_clock_manager.c, function 'alt_clk_pll_vco_chg_methods_get(pll, mult, div);", lines:

    temp = mult * (inputfreq / div);
     if ((temp <= freqmax) && (temp >= freqmin))     // are the final values within frequency limits?

The same values that I read -- not may be written to Clock Manager back !

I has installed last version of updates to SoC EDS 14.0.

If I use "mu/2" as new multiplier, the alt_clk_pll_vco_cfg_set() call is successful, test "my_chk();" works slightly slower.

Use anybody alt_clock_manager.c interface to change main PLL clocks ?