Verilog XOR incorrect result

Question

Hi,

I have a state in state machine where a 2568 bit register is XOR'd with 2568 bit parameter. I tried displaying bits[63:0] of the output in the LCD display. Bits[15:0] of the result is incorrect. I also tried displaying the operands of the XOR operation. They are correct. I don't understand why the output is incorrect.

Please advise.

thanks!

altera_forum · Answer

Your should post some HDL code if you want someone to give you hints

altera_forum · Answer

How's your timing?

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Verilog XOR incorrect result

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