verilog: mux not returning expected output

Hi everyone,

This is my first post, just recently started verilog, so be nice :).

For some reason my I am not getting my expected output.

I think it has to do with yMux producing 2-bits and my I'm expecting a 1-bit output.

(Look below)

mainModule

module mainModule;
	// Registers
	reg flag;
	reg  a, b;
	reg  tem;
	reg c;	
	reg expect;
	
	// Wires
	wire  z;
	
	// Instantiation		
	defparam my_mux.SIZE = 32;
	yMux my_mux(z, a, b, c);
	
	initial	
	begin
		repeat (3) 
		begin 
		 a = $random; 
		 b = $random;  
		 c = $random % 2; 
		# 1;
		 assign tem = (((~ c) & a) | ( c & b));
		 $display("z---->%b", z);
		 
		 $display("eval->%b", tem);
		 expect = (tem === z) ? 1 : 0;    //#1;
		 $display("a:%b, \nb:%b, \nc:%b \n", a, b, c);
		 if (expect === 1)	 
		 	$display("PASS, z->%b", expect, z);
		 else
		 	$display("FAIL, z->%b", expect, z);	
		 	
		 	$display("---------------------------------------------");	
		end 	
		
		$finish;
	end
	
endmodule

yMux

module yMux(z, a, b, c);
parameter SIZE = 2;
output  z;
input  a, b;
input c;
yMux1 mine (z, a, b, c);
endmodule

yMux1

module yMux1(z, a, b, c);
	output z;
	input a, b, c;
	
	wire notC, upper, lower;
	
	not my_not(notC, c);
	and upperAnd(upper, a, notC);
	and lowerAnd(lower, c, b);
	or my_or(z, upper, lower);
endmodule

So in the mainModule I create a register called tem to test and see if it equals z, the output of yMux. But for some reason it sometimes FAILS and SOMETIMES PASSES!! HERE's a sample output:

z---->11000000100010010101111010000001

tem->00010010000101010011010100100101

a:00010010000101010011010100100100,

b:11000000100010010101111010000001,

c:1

FAIL, z->03230228097

---------------------------------------------

Clearly we see that z is not equal to tem?? But why is that!!??