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Altera_Forum
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13 years ago

verilog help case and for loop

Hi guys!, Can I simplify the followingin Verilog?: always@(k) case(k) 0: send_char = node[7+8*0:8*0]; 1: send_char = node[7+8*1:8*1]; 2: send_char = node[7+8...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Curious to know the need for that extra for loop. If you use signal k itself as the start index, you can code:

always@(k)

send_char = node[{k,3'b0} +: 8];