Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

verilog help case and for loop

Hi guys!, Can I simplify the followingin Verilog?: always@(k) case(k) 0: send_char = node[7+8*0:8*0]; 1: send_char = node[7+8*1:8*1]; 2: send_char = node[7+8...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thanks, that did the trick!

The assignment "node[start +: width]" specifies start and width of the sub-vector.

always@(k)

for(i=0; i<10; i=i+1)

if(i==k)

send_char = node[(i*8) +: 8];