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Altera_Forum
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10 years ago

Verilog HDL error : cannot connect instance ports both by order and by name

am doing the SLS SDHC_eMMC card host tutorial enclosed in two jpegs are my code. http://www.alteraforum.com/forum/attachment.php?attachmentid=11741&stc=1 http://www.alteraforum.com/forum/a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

You're missing periods ('.') before some of your instantiated module's signal names.

sdhc_conduit_end_SD_CLK (sdc_clk),

should be

.sdhc_conduit_end_SD_CLK (sdc_clk),

Cheers,

Alex