Verilog HDL coding of "Clock divider by 3"

The problem here is that you are using counters to create logic. it is going to give terrible results (bad results made even worse by the fact your output is the output of logic, not a register).

You should create a clock enable using a single clock. Then everything is on the same clock domain and you wont have any problems related to timing, temperature, voltage and process that you will have with your current implementation.