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Honored Contributor
Honored ContributorVerilog FSM not working on FPGA
Hi, Please accept my appologies if I have posted this is the incorrect place, but im new to this and this post seems kind of relevant. I am trying to create a format for my FSM, To...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- always @(state or count or whatever appears on the right hand side of an expression in that block) --- Quote End --- This suggestion can be basically ignored in synthesis. Although Quartus gives warnings on conditions missing in the always block, the synthesized code won't be different at all. In simulation, the missing trigger in always block most likely causes different behaviour.
