Verilog FSM not working on FPGA

Thans Harald,

I understand what you mean now. I am currently triggering the calculation of next_state at every posedge of clock, ready for the state register to be updated on the negedge of the clock. This does seem to work correclty when synthsised on FPGA.

Would it be better to do this combinationally?

Also if possible could you explain further as to why I cannot write...

//State actions

always @(state)

begin

case(state)

S0: begin

clk_out = 1'b1;

count = 4'b0000;

end

S1: clk_out = 1'd1;

S2: begin

count <= (count + 1'b1);

clk_out = 1'b1;

end

The count does not work correctly, but my understanding of the Verilog is that, whenever state changes value, the construct would be run once. This should update the count register once. And so why is this not possible?

Thanks so much for your help in this matter

Paul

Below is the current working code with all the constructs executed on a clk edge:

module Clock_Gen(rst_n,

clk_out,

clk_in,

count);

//Input Ports

input rst_n;

input clk_in;

//****************************************************

//Output Ports

output [3:0] count;

output clk_out;

//****************************************************

//Output Registers

reg clk_out;

//****************************************************

//Internal Registers

reg [40:0] count;

//****************************************************

//State Definition

parameter S0 = 4'd0,

S1 = 4'd1,

S2 = 4'd2,

S3 = 4'd3,

S4 = 4'd4,

S5 = 4'd5,

S6 = 4'd6;

//****************************************************

//Internal state variables

reg [3:0] state;

reg [3:0] next_state;

//****************************************************

//Set initial reg values

//****************************************************

//State changes only at positive edge of clock (synchronous)

always @(negedge clk_in)

if (!rst_n)

state <= S0;

else

state <= next_state; //State Change

//****************************************************

//State actions

always @(posedge clk_in)

begin

case(state)

S0: begin

clk_out = 1'b1;

count = 25000000;

end

S1: clk_out = 1'd1;

S2: begin

count <= (count - 1);

clk_out = 1'b1;

end

S3: begin

clk_out = 1'b0;

count = 25000000;

end

S4: clk_out = 1'b0;

S5: begin

clk_out = 1'b0;

count <= (count - 1);

end

endcase

end

//****************************************************

//State machine using case statement

always @(posedge clk_in)

begin

case(state)

S0: next_state = S1;

S1: begin

if (count == 0)

next_state = S3;

else

next_state = S2;

end

S2: next_state = S1;

S3: next_state = S4;

S4: begin

if (count == 0)

next_state = S0;

else

next_state = S5;

end

S5: next_state = S4;

endcase

end

endmodule