Verilog FSM not working on FPGA

Hi Paul,

the state of the FSM can only change on the rising clock edge since you clearly define:

always @(posedge clk_in)

if (!rst_n)

state <= S0;

else

state <= next_state;

This is the one and only assignment for the state register. What I mentioned is the calculation of next_state. This, in fact, is the input to the state register, and this is combinational logic depending on the input ports and the state. So, the always construct must be triggered every time one of these signals changes. The first statement assigns the current state to next_state. Depending on this, the case switch is evaluated and a new value for next_state is calculated.