Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Verilog FSM not working on FPGA

Hi, Please accept my appologies if I have posted this is the incorrect place, but im new to this and this post seems kind of relevant. I am trying to create a format for my FSM, To...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Thanks for your reply Harald.

I am unsure about your comment however. Would this not mean that the state would be changed whenever a reg was changed?

I want the FSM to change state synchronously with the clk.

Thanks for your help

Paul