Verilog FSM not working on FPGA

Hi Paul,

even if all works fine now this is not the way I would suggest. Your FSM consists of three parts: State register assignment, state actions, and next_state calculation. This is perfect. However, the next_state calculation lacks two items. The first three lines should be:

always @(state or count or whatever appears on the right hand side of an expression in that block)

begin

case(state)

next_state = state;

...

The always construct also can be written this way

always @(*)

in Verilog 2001. Quartus supports that.