Forum Discussion
Altera_Forum
Honored Contributor
17 years agoVerilog FSM not working on FPGA
Hi, Please accept my appologies if I have posted this is the incorrect place, but im new to this and this post seems kind of relevant. I am trying to create a format for my FSM, To...
Altera_Forum
Honored Contributor
17 years agoBefore using a clock divider created this way, check the cautions for ripple clocks at http://www.alteraforum.com/forum/showthread.php?t=2388.