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Altera_Forum's avatar
Altera_Forum
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17 years ago

Verilog FSM not working on FPGA

Hi, Please accept my appologies if I have posted this is the incorrect place, but im new to this and this post seems kind of relevant. I am trying to create a format for my FSM, To...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Cheers for your reply,

I do get many warnings 337 in fact.

I've changed the always @ (state)

to always @ (negedge clk_in) now - all works fine!

Thanks