Verilog down counter checking for carry

The imagined "single bit check" requires that you have an additional fifth register implemented in your counter.

What you probably didn't yet consider is that the usual fully synchronous counter implementation involves combinational logic to generate the input for each register, it also would for the carry generation. I see this is contrary to how you imagine economical logic, but it's the main stream of FPGA design, for several reasons.

I must confess that I rarely think about describing a delay timer as up or down counter. Sometimes the decision is suggested by additional conditions, sometimes it doesn't matter.