Verilog down counter checking for carry

We are getting off the topic here, but don't take my word for it, look here starting

from 'Synthesis Considerations' which explains why down counters are better:

http://www.bitweenie.com/listings/verilog-counter/

But that is not what I was asking.

I realise this is a small issue, but I'm in the beginning of both this design and my career (if any) as a Verilog coder and I like to get and learn the fundamentals right. Why learn bad habits if you can lear good? There must be a reason why todays code is so bloated, the compressed download of full Quartus Pro is 40 GB!! Maybe if people would pay more attention to what resources they are using world could be a better place. But again we digress.

Parameter does solve the issue of having the counter size in one place, at least partially.

However, consider following:

say I need to count to 11 so my counter is 4 bits but I have to write this as

reg[0:3] and check the bits as rg[3] & rg[1] & rg[0] so my source code nowhere shows the number 11

which was important from the design point of view, neither does it show 4 which is the implementation

size but it shows 3.

Not very good coding practice, at least looking at this from where I come from.

And now I have four places in my code where I can make a mistake where as counting down

I only have two and by calculating the number of bits my counter requires a log(11)/log(2)+1 I can

automate the register size selection and have my code show explicitly the design point of view which

is that the counter counts 11. Of course I would write all that a bit more prettily with parameters and

stuff but I think previous illustrates the point.

But again those are beside the point, my question was simply is the synthesiser smart enough

to recognise that it can implement <0 and >=0 as a single bit check?