Verilog down counter checking for carry

You explanation of up vs. down checking doesn't make sense. With an up counter, like I said, you just have to check one bit. If you're counting to 16, for example, when the counter equals "10000", the MSB is high and you overflow. You don't need to do any of the stuff you're talking about.

Worrying about hardware use with logic this simple is not something you should be concerned about either unless you are using a really old, small FPGA or your design is so massive (filling 80 to over 90% of the device) that you are looking for any little thing you can to reduce resource usage (which there are many other places to look at to reduce resource usage than this).

As far as the size of the counter changing, just use a parameter for the counter width. That way you only have to make a change in one spot at the top of the design file.