Verilog down counter checking for carry

Hi,

thanks for looking into this.

Going down and checking the MSB uses the least resources because checking the end of count

only requires checking one bit, the sign. This is regardless of what the re-load value is.

Going up you need to check with multiple and/xor logic for the end of count value OR

you have to reload with a value that is the size of the counter minus the count you want,

which is even uglier.

So going down is definitely better from resource use point of view (at least in the hardware

level) and IF the checking the MSB can be done as <0 or >=0 then that is also better

that checking the MSB explicitly because if I need to write the MSB bit number there I can make a mistake

if/when the counter size changes. If I check the MSB explicitly I need to change the counter size

in two places in the source code which is not as clean and maintainable as having it only in one place.

My background is software so I tend to look at this perhaps from the good source code style point of view more than a hardware guy would.