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I think it is the large array that is causing my problem
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That sounds plausible, because the implementation will need a large amount of combinational logic to mux and demux data to each of the 4096 memory bits.
Using internal RAM is the obvious solution, involving a much smaller logic utilization footprint. You have to keep the requirements for RAM inference however. The most serious restriction is, that at maximum two (in case of a dual port RAM) memory addresses can be accessed at a time, also the synchronous character of memory access must be observed.
To get an idea how it works, you can use the VHDL or Verilog RAM usage templates available in the Quartus IDE.
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