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Altera_Forum
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14 years ago

vdhl code for 7segment display

i am writing a vhdl code at the moment, am trying to display no 1234 on a 7 segment display but at different times with delay but most time it shows the output at the same time. can anyone help me w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

library ieee;

use ieee.std_logic_1164.all;

entity seq2_tb is

end seq2_tb;

architecture test of seq2_tb is

signal A: std_logic;

signal s: bit_vector ;

signal B : std_logic;

signal C: std_logic;

begin

instance1: entity work.seq2(Timer)

port map (PB=>A, X=>S ,clk =>B , reset=>C);

S<="1001111" after 10 sec;

S<="0110010" after 15 sec;

S<="0000110" after 20 sec;

S<="1001100" after 25 sec;

S<="0100100" after 30 sec;

S<="01100" after 35 sec;

end test;

Another test bench i wrote.