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Altera_Forum
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16 years ago

Variable Frequency of clk

i have a design that require to run on variable frequency of clk(sampling rate), in the range of 8kHz to 216kHz. My question are: 1. How to write the sdc? 2. Other than sdc, is there any ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Actually, the pll inside can't handle the the sampling freq, fs like 44.xxxx kHz where the internal PLL(FPGA) can't divide it to the required freq(with fix point) due to limited no. of bits of multiplier and divider(9 bit).

In order to fix it, it need a PLL (with more than 9 bit), dsp chip to divide and multiply.

thanks