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Honored Contributor
Honored ContributorVariable Frequency of clk
i have a design that require to run on variable frequency of clk(sampling rate), in the range of 8kHz to 216kHz. My question are: 1. How to write the sdc? 2. Other than sdc, is there any ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Different clock divider will run on different module --- Quote End --- I think, it should handle the internal timing as well. But this fact increases my doubts about your "system architecture" being well considered. (I'm tempted to call it a "no-architecture"). Check the results and be prepared to reconsider the design in time.
