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Altera_Forum
Honored Contributor
Honored ContributorVariable Frequency of clk
i have a design that require to run on variable frequency of clk(sampling rate), in the range of 8kHz to 216kHz. My question are: 1. How to write the sdc? 2. Other than sdc, is there any ...
Altera_ForumHonored Contributor
Honored ContributorFvM,
Different clock divider will run on different module. So, there are signal across different time domain. In this state, classical timing analysis is still useful for my case?
