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Altera_Forum's avatar
Altera_Forum
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16 years ago

Variable Frequency of clk

i have a design that require to run on variable frequency of clk(sampling rate), in the range of 8kHz to 216kHz. My question are: 1. How to write the sdc? 2. Other than sdc, is there any ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The system architecture is decided. It is impossible for me to change it.

FYI, The system clock is changed on the fly once the user enter through GUI. I think that there is no problem in digital design since it is just connected to the pin of register. Some delay may impact.

The problem is i have no idea to proceed with the Time Quest Analysis without knowing the method to write the sdc file.

Any help will be appreciated.