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Honored Contributor
Honored ContributorVariable Frequency of clk
i have a design that require to run on variable frequency of clk(sampling rate), in the range of 8kHz to 216kHz. My question are: 1. How to write the sdc? 2. Other than sdc, is there any ...
Altera_ForumHonored Contributor
Honored ContributorThe suggestion is to use a fixed system clock (e.g. 50 MHz) and a variable rate clock enable. The timing requirements don't change with the clock enable rate.
