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Altera_Forum's avatar
Altera_Forum
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16 years ago

Variable Frequency of clk

i have a design that require to run on variable frequency of clk(sampling rate), in the range of 8kHz to 216kHz. My question are: 1. How to write the sdc? 2. Other than sdc, is there any ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

However, my system clk is changing according to n(integer) X fs. Don't you think to add timing constraint?

if yes, how?

if no. thanks