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Altera_Forum
Honored Contributor
Honored ContributorVariable Frequency of clk
i have a design that require to run on variable frequency of clk(sampling rate), in the range of 8kHz to 216kHz. My question are: 1. How to write the sdc? 2. Other than sdc, is there any ...
Altera_ForumHonored Contributor
Honored ContributorI would expect the "variable frequency" sampling clock implemented as a synchronous clock enable, generated by a clock divider. In this case, no additional timing constraints are involved, because the timing is completey based on the system clock.
