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Fpga_Egr_2025's avatar
Fpga_Egr_2025
Icon for Occasional Contributor rankOccasional Contributor
1 day ago

UVM Questasim simulation

HI , I am trying to simulate a generic ALU in Systemverilog UVM test environment . My add_i is random input signal , but when i open my wave i dont see it toggling , but the display function reports...
Core Logic
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
5 hours ago

Hi,

In the alu_pkg.sv posted, you may change //vif.add_i <= 1; to vif.add_i <= trans.add_i;       and        

//vif.add_i <= 0; to vif.add_i <= 0; (for clearing purpose this is optional) then you may get below waveform:

Attached file for your reference.