Altera_Forum
Honored Contributor
8 years agoUtilizing tristate (bi-directional) pins
I have a i2c master component, the i2c lines (SDA, SCL) are tristate, either pulling the physical pin down, or to Z state. The simulation is working well, and now I am making my own component in Qsys. My question is, how to export these 2 lines (SDA, SCL), is their interface a "conduit" or "tristate conduit master" ?. I have checked the documentation (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_avalon_tc.pdf), and it seems to me, that TCM (Tristate Conduit Master) is a special piece of hardware with avalon inside FPGA, and tristate bi-directional pins on the "outside", this is not my case, as I have my own logic inside the core.
definition of signals in my VHDL code is as follows : scl <= scl_pad_o when (scl_padoen_o = '0') else 'Z'; sda <= sda_pad_o when (sda_padoen_o = '0') else 'Z'; scl_pad_i <= scl; sda_pad_i <= sda; does the above VHDL code implies tristate behaviour of the external pins, when I declare the "sda" and "scl" signal with "conduit" interface and export them in Qsys ? Or do I need to break the above signals into "scl_pad_o", "scl_pad_i" and "scl_padoen_o" to export them under tcm interface ? I would be glad to know more about interfacing with physical pins, and also whether Qsys understands these implications in VHDL (as above). And what the "conduit" interface is actually capable of.