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Altera_Forum
Honored Contributor
Honored ContributorUsing Timequest to Analyze Processor Bus Interface
We have a design with a processor connected to the FPGA using standard address, data and control signals. This processor uses an internal clock of 200 MHz to control these signals and we have a 200 ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Hi Kaz, Thanks for the response but I was hoping this wouldn't be the answer. I presume that in your description above, we need standard 2 flop synchronizer for address and data. I was thinking that maybe a pipelined compare and decode might do the trick for address but that might still be susceptible to metastability. Thoughts? --- Quote End --- Typically for a bus like this (address and data timing related to some control signal) a two stage synchronizer is only required on the 'master' bus cycle control signal that is asserted to start (ie, falling edge) and to end (ie, rising edge) a bus transaction. Address/data/mode are then specified with a known setup before cycle start, and hold after cycle end that allows only a signal rank of registers to be used to capture valid address/data/etc.
