Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorUsing Timequest to Analyze Processor Bus Interface
We have a design with a processor connected to the FPGA using standard address, data and control signals. This processor uses an internal clock of 200 MHz to control these signals and we have a 200 ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Hi Kaz, Thanks for the response but I was hoping this wouldn't be the answer. I presume that in your description above, we need standard 2 flop synchronizer for address and data. I was thinking that maybe a pipelined compare and decode might do the trick for address but that might still be susceptible to metastability. Thoughts? --- Quote End --- I really don't see any other solution. two stage is tiny resource in many fpgas. you will need two registers + 1 delay for rd signal. registers for address and data synchronisers and a third set for addres/data to enable sampling on rd. For wr and wrdata to processor that is not fpga responsibility but processor's and I don't see what you can do here apart from slowing down transfers. So in principle this interface is asynchronous and reminds me of RS232 ...etc. which need its own protocol on either side.
