Using SDRAM

Thanks for your comments, Cris72, Socrates and K_J

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Option 1 (Instantiate another SDRAM controller) isn't an option. You have only one SDRAM, therefore you can have only one SDRAM controller.

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Would this really be impossible? I was thinking we could possibly multiplex the signals between the 2 SDRAM controllers, since the read and write operations are separate. That is, we use a signal/flag that tells us whether we are writing or reading from SDRAM, and using that signal to choose the addr, data, write_select, etc. signals from the controller in SOPC while in write mode, and then choose signals from the other controller when in "read" mode.

I haven't done it before though, so I'm not quite sure what complications might arise.

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Your comment about option 2 being less desirable because "many custom written HDL modules that were written from when a camera was interfaced directly to the GPIO pins on my devkit" makes me think that your current HDL interface might simply be expecting a stream of data as input and there currently is no memory interface. If that is the case, then the best approach is the following:

- Basically leave the HDL modules alone assuming that they at least have some form of 'data valid' input that is used to mark incoming camera data as being valid. This preserves your existing investment in your existing modules as much as possible.

- Write a simple DMA controller to provide the addressing to the SDRAM Controller via an Avalon master interface and supplies a stream of output data via an Avalon slave interface or streaming data interface. This slave or streaming data interface becomes the input to your HDL modules.

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Yes you are correct. This is exactly my situation. This seems to be the way to go, at least for now. I'm afraid I'm not very familiar with DMA, though. Do you think it's straightforward enough to quickly write one myself, or do you suggest I use the megacore?

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Option 3 doesn't make any sense at all.

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Actually, I was thinking of something like the NIOS II UDP Offload Example while searching around for solutions:

alterawiki DOT com/wiki/Nios_II_UDP_Offload_Example

(sorry, for some reason I can't post links)

Basically we want UDP packets to be handled by a hardware path, and use either NIOS II or a state machine to do initialization etc. of the TSE MAC and ethernet PHY. This has several benefits:

1) Probably a lot faster than if NIOS II handles the packets

2) I get to do some processing on the streaming data with my HDL modules before it gets saved into the SDRAM

I'm not nearly familiar enough with the TSE MAC though, so I was hoping someone could shed light on how easily I could this. I would think UDP is pretty straightforward.