Using SDRAM

Option 1 (Instantiate another SDRAM controller) isn't an option. You have only one SDRAM, therefore you can have only one SDRAM controller.

Option 2 is probably closest assuming that what you have in your HDL modules expects to read from memory. If that is the case, then you simply need to modify that memory interface to be Avalon compliant and get it connected to the SDRAM controller. SOPC can provide the arbitration between the current master and the master for your HDL modules or you can write that arbitration yourself. All this means for the HDL modules that you have is that you need to:

- Accept a 'Wait' input on the address/command signal outputs to hold the address and read/write commands whenever 'Wait' is active

- Accept a 'ReadDataValid' input on the read data signals to flag when the data is actually valid.

Whether or not this is a lot of work or not, depends on what your current HDL's memory interface looks like. However, I'll also point out that your custom HDL should've been written in the first place to have a generic memory interface to start with. If it doesn't now would be a good time to do so since then you'll be able to port it easily in the future to other memory systems (i.e. DDR/2/3, etc.)

Option 3 doesn't make any sense at all.

Your comment about option 2 being less desirable because "many custom written HDL modules that were written from when a camera was interfaced directly to the GPIO pins on my devkit" makes me think that your current HDL interface might simply be expecting a stream of data as input and there currently is no memory interface. If that is the case, then the best approach is the following:

- Basically leave the HDL modules alone assuming that they at least have some form of 'data valid' input that is used to mark incoming camera data as being valid. This preserves your existing investment in your existing modules as much as possible.

- Write a simple DMA controller to provide the addressing to the SDRAM Controller via an Avalon master interface and supplies a stream of output data via an Avalon slave interface or streaming data interface. This slave or streaming data interface becomes the input to your HDL modules.

Kevin Jennings