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Jerry,
1. The DCO LVDS signal is the high-speed output clock from the ADC. In Cyclone devices the easiest way is to use them as the IO-clock. I extrapolate this would also come easy in Stratix devices. The other way may be to use an internally PLL-generated clock and dynamically set the delay in the input cells to align the data with this clock. I haven't tried this as in Cyclone this definitely is not possible, but I think this could work in Stratix devices.
2. At the time I fed 4 octal 12-bit ADCs into an EP2C8F256. I had 4 of these feeding further into an EP2SGX60 (making 16 ADCs or 128 analog channels in total). This is the only time I used Stratix FPGA's.
http://www.alteraforum.com/forum/attachment.php?attachmentid=13050&stc=1 I used the DCO of each ADC to clock in the data, and connected each DCO to a (regional) clock input.
3. How many ADC devices do you want to connect to which Stratix IV GX device?
Regards,
Josy
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Hello Josy,
Thanks for you reply.
1. Can DCO connect to IO-clock, which doesn't locate in the same IO-bank of the normal ADC output data lvds siganls connected?
2. There are 16 ADC clocks (DCO) that need to be connected to your EP2S60, and all of these DCO are connected to EP2S60's clock-IO, am i right?
3. I have 12 ADC devices. And my FPGA have total 16 normal clock-IO, exclude transceiver ref-clock. I don't think i can connect DCO to those transceiver ref-clock pins. My ADC PN is AD9633 and i want it run at 100M@10-bits, so the DCO output clock speed will be 500MHz.
BTW, When you place and route your ADC channels, did you make trace length equal constrain among all DCO signals and among all ADC output lvds signals? Is this trace length equal control necessary?
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