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1. Must DCO be connected to clock input?
2. Does your FPGA has 8 pair LVDS clock input pins? What's your fpga PN? For you said, you have processed several octal channels ADCs, in single FPGA?
3. My fpga only has 4 pairs dedicated LVDS clocks, which on left and right sides of the FPGA. Can i connect dco to dedicated clock input pins on top or bottom sides of the FPGA? And configure them as LVDS input.
The PLL_[L1,L4,R1,R4]_CLK* are the LVDS module dedicated clock, which will feed to the dedicated PLL. Also, this FPGA has many other normal clock input pins, as below figure shows. My question is that can i connect the ADC DCO signals to these clock input pins regardless of where they are (top or bottom or left or right sides)?
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Jerry,
1. The DCO LVDS signal is the high-speed output clock from the ADC. In Cyclone devices the easiest way is to use them as the IO-clock. I extrapolate this would also come easy in Stratix devices. The other way may be to use an internally PLL-generated clock and dynamically set the delay in the input cells to align the data with this clock. I haven't tried this as in Cyclone this definitely is not possible, but I think this could work in Stratix devices.
2. At the time I fed 4 octal 12-bit ADCs into an EP2C8F256. I had 4 of these feeding further into an EP2SGX60 (making 16 ADCs or 128 analog channels in total). This is the only time I used Stratix FPGA's.
https://www.alteraforum.com/forum/attachment.php?attachmentid=13050 I used the DCO of each ADC to clock in the data, and connected each DCO to a (regional) clock input.
3. How many ADC devices do you want to connect to which Stratix IV GX device?
Regards,
Josy
Honored Contributor
