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Jerry,
you connect the DCO signals to LVDS clock input pins on the FPGA.
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1. Must DCO be connected to clock input?
2. Does your FPGA has 8 pair LVDS clock input pins? What's your fpga PN? For you said, you have processed several octal channels ADCs, in single FPGA?
3. My fpga only has 4 pairs dedicated LVDS clocks, which on left and right sides of the FPGA. Can i connect dco to dedicated clock input pins on top or bottom sides of the FPGA? And configure them as LVDS input.
http://www.alteraforum.com/forum/attachment.php?attachmentid=13048&stc=1 The PLL_[L1,L4,R1,R4]_CLK* are the LVDS module dedicated clock, which will feed to the dedicated PLL. Also, this FPGA has many other normal clock input pins, as below figure shows. My question is that can i connect the ADC DCO signals to these clock input pins regardless of where they are (top or bottom or left or right sides)?
http://www.alteraforum.com/forum/attachment.php?attachmentid=13049&stc=1
Honored Contributor
