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I didn't yet observe the reported warning and don't know why it's generated in your design. May be it's due to the ad_in2_tmp wire signal.
Actually Cyclone IV uses LE registers for ddio_in, so the warning is irrelevant in any case.
You should primarly look for succesful timing closure and first of all correct operation of actual hardware design.
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Thx for ur reply. Shortly, I have two questions as follow:
- Could the input of ALTDDIO_IN connect the I/O input signal directly? Or the input of ALTDDIO_IN should connect particular I/O pin? When I connect I/O pin to ALTDDIO_IN directly, I got the following Warning.
Warning (176225): Can't pack node ad_ddio_in:inst_ad_ddio_in|altddio_in:ALTDDIO_IN_component|ddio_in_1di:auto_generated|input_cell_l to I/O pin
- I don't know if I should source synchronize the AD data clock(DCO) and the AD output(ad_in2). If I use a PLL to creat a clock(dco_clk) in source synchronous mode, I should do PLL compensation in Assignment Editor, or I will get this warning.
Warning (15062): PLL "ad_pll:inst_ad_pll|altpll:altpll_component|ad_pll_altpll:auto_generated|pll1" in Source Synchronous mode with compensated output clock set to clk is not fully compensated because it does not feed an I/O input register
So I added the following codes and the above warning dispears. process(dco_clk)
begin
if(rising_edge(dco_clk)) then
ad_in2_reg <= ad_in2;
end if;
end process;
But in this way, I can only get the partial data of (ad_in2) because it's DDR output. So I don't know what should I do to figure this out.Could u give me some suggestions plz?
Or could u give me a way about how to get the DDR data of AD9252 using EP4CE115F29? Many thanks!
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