using lvds

AD9252 is basically similar to AD9222, expect for a resolution of 14 versus 12 bit.

I completely agree with josyb about the suggested solution (DDIO + shift register). Also the deserialization factor of 14 is correct. Strictly spoken, you won't necessarily need a PLL for the receiver, because the ADC provide both fast and slow (respectively bit and frame) clock. but, 700 Mbps is pretty on the edge, a means to adjust the clock phases manually may turn out to be badly required. A receiver PLL would use the frame clock (FCO) as input clock and generate the fast clock. You can also connect both ADC clocks to the FPGA and keep all options.

See below a VHDL example of 4-channel 14-Bit ADC receiver, that can be easily changed to 8 Channels.

chan:
FOR I IN 0 TO 3 GENERATE
	lvds_rcv : altddio_in
	GENERIC MAP (
		intended_device_family => "Cyclone III",
		invert_input_clocks => "ON",
		lpm_type => "altddio_in",
		power_up_high => "OFF",
		width => 1
	)
	PORT MAP (
		datain => AD9259_D(I DOWNTO I),
		inclock => fastclock,
		dataout_h => dataout_h(I DOWNTO I),
		dataout_l => dataout_l(I DOWNTO I)
	);
	PROCESS (fastclock)
	BEGIN
      IF rising_edge(fastclock) THEN
         lvds_sr(I) <= lvds_sr(I)(11 downto 0) & dataout_l(I) & dataout_h(I);
		END IF;
	END PROCESS;
	PROCESS (slowclock)
	BEGIN
	   IF reset = '1' THEN
	      lvds_rx(I) <= (others => '0');
      ELSIF rising_edge(slowclock) THEN
         lvds_rx(I) <= lvds_sr(I);
		END IF;
	END PROCESS;
END GENERATE;