Using LVDS channels in the same bank driven by separate PLLs

Basically, in an IO bank you have pins like:

PLL_T

0 <->

1 <->

2 <->

3 <->

PLL_B

In this, all 0 to 3 RX channels can be driven by one PLL, and all of the TX channels can be driven by the other.

Alternatively, channels 0 and 1 can be driven by PLL_T (both RX and TX). Channels 2 and 3 can be driven by PLL_B at the same time (both RX and TX)

However, channels 0 and 2 can't be driven by PLL_T if channels 1 and 3 are being driven by PLL_B. In otherwords they can't be interleaved.

So the following configurations work:

(A)

0 <=> PLL_T

1 <=> PLL_T

2 <=> PLL_T

3 <=> PLL_T

(B)

PLL_B <= 0 <= PLL_T

PLL_B <= 1 <= PLL_T

PLL_B <= 2 <= PLL_T

PLL_B <= 3 <= PLL_T

(C)

0 <=> PLL_T

1 <=> PLL_T

2 <=> PLL_B

3 <=> PLL_B

But the following will not work:

(D)

0 <=> PLL_T

1 <=> PLL_B

2 <=> PLL_T

3 <=> PLL_B

(E)

0 <=> PLL_T

1 <=> PLL_B

2 <=> PLL_B

3 <=> PLL_T